1. Field of the Invention
The invention relates to a non-volatile semiconductor memory device and more particularly to a programming method and an erasing method of a flash memory.
2. Description of the Related Art
A NAND type flash memory comprises a memory array consisting of a plurality of NAND strings arranged in a matrix form. One NAND string comprises a plurality of memory cells connected in serial and select transistors provided at two ends of the NAND string. One end of the NAND string is connected to a bit line through one of the select transistors, and the other end of the NAND string is connected to a source line through the other one of the select transistors.
A conventional memory cell comprises an N-type source, an N-type drain, an oxide film formed on a channel defined between the source and the drain, a floating gate (charge accumulation layer) formed on the oxide film for accumulating charges, and a control gate formed on the floating gate through a dielectric film. When a programming (write-in) operation is performed, a high voltage is applied to the control gate and 0V is applied to the channel. As such, electrons pass through the oxide film by Fowler-Nordheim tunneling (F-N tunneling) and are accumulated in the floating gate. When electrons are accumulated in the floating gate, that is, when data “0” is stored, a threshold value is shifted toward a positive value and the memory cell is normally off. On the other hand, when an erase operation is performed, a high voltage is applied to a P-well region and 0V is applied to the control gate. As such, electrons accumulated in the floating gate pass through the oxide film by F-N tunneling and are pulled to a substrate. When the floating gate doesn't accumulate charges, that is, when data “1” is stored, the threshold value is a negative value and the memory cell is normally on.
As described above, in the programming operation, the floating gate accumulates electrons and the threshold voltage of the memory cell is shifted toward a positive value, while in the erase operation, electrons are released from the floating gate and the threshold voltage of the memory cell is shifted toward a negative value. Therefore, the programming operation and the erase operation have to be controlled so that the threshold value of the memory cell can be within distribution widths of “0” and “1”. Moreover, if the memory cell stores multiple bits, the programming operation and the erase operation have to be controlled so that the threshold value of the memory cell can be within distribution widths of “00”, “01”, “10” and “11”.
Nevertheless, since sizes and shapes of memory cells vary according to changes in process parameters and the number of times of programming and erasing is a main cause of deterioration of oxide films, it is not easy to erase data in the memory cells. In other words, in some memory cells, electrons are easy to be released and thus threshold values are easy to be within the threshold value distribution width of “1”, while in some other memory cells, electrons are not easy to be released and thus some threshold values may not be within the threshold value distribution width of “1”. In view of this, if it is detected by an erase verify operation that there is a memory cell in which electrons are not completely released, the erase voltage has to be applied to the selected block again to make the threshold value of the memory cell be within the threshold value distribution width of “1”.
In order to correctly and effectively release electrons from memory cells, an ISPE (Incremental Step Pulse Erase) method is usually used. As shown in FIG. 1A, in the ISPE method, an initial erase pulse Vers0 is applied to memory cells in a selected block. If it is detected by an erase verify operation that there is an unqualified erase operation, an erase pulse Vers1 that is one step voltage higher than the initial erase pulse Vers0 is applied. The voltage of the erase pulse is incremented sequentially until erase operations of all memory cells in the block are all qualified.
Similarly, when programming, it is hard to make floating gates of all memory cells in a page all accumulate electrons evenly. In some memory cells, electrons are easy to be poured into floating gates, while in some other memory cells, electrons are not easy to be poured into floating gates. Therefore, if the same programming voltage is applied to the two kinds of memory cells, threshold value shift amounts of the two kinds of memory cells will be quite different. For example, in some memory cells, electrons are sufficiently accumulated in floating gates and thus threshold values can be within the threshold value distribution width of “0”, while in some other memory cells, electrons are insufficiently accumulated in floating gates and thus some threshold values may not be within the threshold value distribution width of “0”. In view of this, if it is detected by a program verify operation that there is a memory cell in which electrons are insufficiently poured into the floating gate of the memory cell, the programming voltage has to be applied to the memory cell again to make the threshold value of the memory cell be within the threshold value distribution width of “0”.
In order to correctly and effectively pour electrons into memory cells, an ISPP (Incremental Step Pulse Program) method is usually used. As shown in FIG. 1B, in the ISPP method, an initial programming pulse Vpgm0 is applied to a selected page. If it is detected by a program verify operation that there is an unqualified programming operation, a programming pulse Vpgm1 that is one step voltage higher than the initial programming pulse Vpgm0 is applied. The voltage of the programming pulse is incremented sequentially until programming operations of all memory cells in the page are all qualified.
Moreover, due to the high integration of the flash memory, sizes of memory cells become smaller, and resistances of word lines and bit lines become larger because of fine sizes of the word lines and the bit lines. Thus, voltage drops on the word lines and the bit lines become larger. Accordingly, a problem that charging time of the word lines and the bit lines increase may occur. In Patent Document 1, in order to reduce data write-in time, preliminary data whose temporary level is lower than the level of the threshold voltage is written-in, and a write-in verify operation is performed on read-out data. The waiting time of word lines at this time is smaller than the waiting time when reading-out final data in a write-in verify operation.